Recent advancement in semiconductor manufacturing techniques has led to increasingly small design criteria. For example, semiconductor devices such 1-Gbit DRAMs have proceeded to a size where alignment margin can hardly be secured when aligning a contact plug with a semiconductor layer or an interconnect layer underlying the contact plug. For a 1-Gbit DRAM having a design criterion of 0.45 .mu.m pitch or less, the maximum permissible line space is very small, and the size of the contacts must be 0.15 .mu.m or less. Because of the small sizes, using the conventional direct contact method to form a bit contact or a contact for a storage nodes is difficult. Accordingly, a manufacturing process that self-aligns the contact plug with a semiconductor layer or an interconnect layer underlying the contact plug is employed for sub-quarter micron semiconductor devices. The resulting self aligned contact (SAC) has the advantages of allowing increased margin for misalignment during photolithography and reducing contact resistance.
However, as the pattern sizes become smaller, the possibility of a short between a contact hole and a gate line increases. The contact hole aspect ratio, defined as contact width over contact height, for a high integration density device, such as a memory device, inevitably becomes high. As a result, an etch stop phenomenon occurs during the contact hole formation.
A proposed solution to overcome the etch stop phenomenon uses contact pads. FIG. 1 and FIG. 2 show a conventional method for forming contact holes using SAC pads. FIG. 1 is a top plan view showing an a conventional SAC pad structure, and FIGS. 2A and 2B are cross-sectional views taken along line I-I' of FIG. 1, illustrating process steps for SAC pad formation.
Referring to FIG. 2A, a device isolation region 3 is formed over a semiconductor substrate 1 to define active region 2 and an inactive region. Device isolation region 3 is formed by a suitable method well known in the art, for example, shallow trench isolation (STI) and local oxidation of silicon (LOCOS). A gate oxide layer (not shown) is formed by a conventional method such as thermal oxidation. A gate electrode conductive layer is deposited over the gate oxide layer. A gate mask insulating layer is then formed over the gate electrode conductive layer. The gate electrode conductive layer is generally laminated with polysilicon and tungsten silicide. The gate mask insulating layer is composed of a silicon nitride layer or a silicon oxynitride layer which has an etch selectivity ratio with respect to a subsequent interlayer dielectric layer 6. A gate electrode structure 4 consisting of gate electrode 4a and gate mask layer 4b is formed from the electrode conductive layer and the gate mask layer by conventional photolithography.
Low concentration impurity ions are implanted into active region 2 of semiconductor substrate 1 not covered by gate electrode structure 4, forming a low concentration source/drain region for a LDD (lightly doped drain) structure. Gate spacer 5, which has an etch selectivity ratio with respect to a subsequent interlayer dielectric layer 6, is formed on the sidewalls of gate electrode structure 4. Gate spacer 5 is generally silicon nitride or silicon oxynitride. High concentration impurity ions are then implanted into active region 2 of semiconductor substrate 1 not covered by gate spacer 5 or gate electrode structure 4 to form high concentration source/drain regions. A transistor having LDD structure is thereby formed.
Next, interlayer dielectric layer 6 is deposited over semiconductor substrate 1. A photoresist pattern (not shown) for a self aligned contact is then formed over interlayer dielectric layer 6. Interlayer dielectric layer 6 is then masked and etched using the photoresist pattern, forming contact holes 7a and 7b.
Referring to FIG. 2B, the photoresist pattern is removed, and contact holes 7a and 7b are filled with a conductive material such as polysilicon. The conductive material layer is then planarized using planarization processes well known in the art, such as a CMP (chemical mechanical polishing) and etch-back processes. The planarization process leaves the self aligned storage node contact pad 8a and bit contact pad 8b. For high density devices having a 0.45 .mu.m pitch or less, performing photolithography to form contact holes 7a and 7b is difficult because contact holes 7a and 7b must be laterally electrically isolated from each other. Thus, interlayer dielectric layer 6 has a very narrow width W, as shown in FIG. 2A.
The self aligned contact pattern for the above described conventional method for forming SAC pad is either circular or elliptical, as shown in FIG. 1. As the device pattern becomes smaller, the area to be etched decreases, and the contact hole aspect ratio increases. As a result, the etching rate falls with the depth of the hole because etching by-products such as polymers cannot easily diffuse out of the contact holes. In severe cases, the etch stop phenomenon occurs where etching by-products in the holes significantly reduce the etching rate or even stop further etching.
To the prevent the etch stop phenomenon, etching must be performed under conditions that suppress by-product formation. In addition, etching time must be increased. However, such etching etches the gate mask layer and sidewall gate spacer and can create a short between the SAC pad and the gate.
Y. Kohyama et al. proposed a method for forming SAC pads in an article entitled "A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1-Gbit DRAM and Beyond", Symp. on VLSI Tech., digest of technical papers, pp. 17-18, 1997. The article discloses a gate SAC pattern (which indicates resist area) that is the same as the active area and is shifted by a half pitch in the gate direction. Because the photoresist pattern area is very small, polymer formation is very low during formation of the contact holes. Consequently, the etch selectivity ratio of the interlayer dielectric layer to the nitride layer of the gate spacers and the gate mask layer becomes low. The low selectivity ratio results because polymer formation is proportional to the photoresist pattern area and is inversely proportional to the etching selectivity ratio.
What is needed is a method for forming a self aligned contact in a semiconductor structure that prevents the etch stop phenomenon and has a good etch selectivity ratio during the etching that forms the self-aligned contact openings.